What I'm saying is this, and this is all I have been saying. Say there is
one defect on a wafer and there are four chips covering it. The yield is
75%. Now say there is one defect on a wafer and there are 100 chips covering
it. The yield is 99%. That's a no brainer. I don't care what your process is
(small or large), etc. etc. etc. This is just math.
Frank Paris
marshalt@spiritone.com
> -----Original Message-----
> From: owner-filmscanners@halftone.co.uk
> [mailto:owner-filmscanners@halftone.co.uk]On Behalf Of Austin Franklin
> Sent: Thursday, February 01, 2001 6:01 AM
> To: filmscanners@halftone.co.uk
> Subject: RE: Future of Photography (was filmscanners: real value?)
>
>
> Frank, I design ASICs, and have designed well over 100 of them, so I know
> what I say IS true. What you say about scaling the die (pure geometry) IS
> correct, and in fact is something I said in one of my posts. But
> that does
> not make a different (smaller or larger) process give a higher yield, they
> are two different things.
>
> Typically, the "older" processes, which are larger processes, are what
> companies make their high volume, less expensive parts from,
> simply because
> they get a much higher yield from them.
>
>
> > -----Original Message-----
> > From: owner-filmscanners@halftone.co.uk
> > [mailto:owner-filmscanners@halftone.co.uk]On Behalf Of Frank Paris
> > Sent: Thursday, February 01, 2001 1:02 AM
> > To: filmscanners@halftone.co.uk
> > Subject: RE: Future of Photography (was filmscanners: real value?)
> >
> >
> > I work for an IC testing company (Credence Systems) and I
> > know that what
> > you're saying isn't true. In fact, it's just pure geometry.
> > You don't even
> > have to understand the physics of it.
> >
> > Frank Paris
> > marshalt@spiritone.com
> >
> >
> > > It isn't true that because the die is
> > > larger simply because of process size, that the yield goes
> > > down...in fact it
> > > typically goes up.
> > >
> >
>
